1. Field of the Invention
The present invention relates to an odd-number frequency divider for frequency dividing an input signal of optional frequency, and more particularly to a frequency divider for outputting a digital frequency-divided signal having a frequency division ratio of 1/[2n+1] (n is an integral number) and a duty ratio of 50% with respect to the input signal and a method of constituting the frequency divider.
2. Description of the Related Art
In recent years, an integrated circuit for receiving a clock signal of high frequency and operating at a high speed is designed with the demand for high performance and high function of an information processing unit. An odd-number frequency divider circuit generating a digital frequency-divided signal having a frequency division ratio of 1/[2n+1] is incorporated in the integrated circuit concerned. This digital frequency-divided signal is used, for example, for timing control of various function circuits.
Here, a prior art related to the present invention will be described. For example, a ternary counter is composed of flip-flop circuits F1 and F2 and a two-input NOR circuit 1 as shown in FIG. 1. The ternary counter receives a clock signal CK and outputs a non-inverted counter output signal (hereinafter referred to simply as a non-inverted output signal QB) of a one-third frequency division ratio.
Namely, the function of the circuit concerned is such that a non-inverted output signal QA is generated when the clock signal CK is frequency-divided into one half by the flip-flop circuit F1 as shown in a truth table in FIG. 1 and an operational waveform diagram in FIG. 2. Further, in the flip-flop circuit F2, an inverted counter output signal (hereinafter referred to simply as an inverted output signal QA) is received and a non-inverted output signal QB is generated.
The inverted output signal QA of the flip-flop circuit F1 and the inverted output signal QB of the flip-flop circuit F2 are inputted to the NOR circuit 1. With this, a reset signal SR is generated from the NOR circuit 1. This reset signal SR is supplied to the flip-flop circuits F1 and F2.
Thus, a non-inverted output signal QB such as shown in FIG. 2C is outputted from the flip-flop circuit F2. This signal QB has a frequency division ratio at 1/3 and a duty ratio K at approximately 33%. Here, it is assumed that the duty ratio K means a ratio of a period of an "H" level or a period B of an "L" level to one period (A=1) of the object signal.
Further, a quinary counter related to a conventional example is composed of flip-flop circuits F3, F4 and F5 and a NOR circuit 2 as shown in FIG. 3. For example, the quinary counter receives a clock signal CK and outputs a non-inverted output signal QC. The signal QC concerned has a one-fifth frequency division ratio.
Namely, the function of the counter concerned is such that a non-inverted output signal QA is generated when the clock signal CK is frequency-divided into one half by the flip-flop circuit F3 as shown in a truth table in FIG. 3 and an operational waveform diagram in FIG. 4. Further, when the inverted output signal QA is inputted to the flip-flop circuit F4, a non-inverted output signal QB is generated.
When the inverted output signal QB is inputted to the flip-flop circuit F5, a non-inverted output signal QC is generated. When the inverted output signal QA of the flip-flop circuit F3 and the inverted output signal QC of the flip-flop circuit F5 are supplied to the NOR circuit 2, a reset signal SR is generated. This reset signal SR is supplied to the flip-flop circuits F3, F4 and F5.
With this, the non-inverted output signal QC as shown in FIG. 4D is outputted from the flip-flop circuit F5. The signal QC has a frequency division ratio of 1/5 and a duty ratio K of 20%. In the ternary counter and the quinary counter according to a conventional example, however, it is impossible to obtain a digital frequency-divided signal having a duty ratio of 50%.
Next, a structural example of an odd-number frequency divider for outputting a digital frequency-divided signal having a duty ratio of 50% will be presented. A digital frequency division circuit is disclosed in Provisional Publication No. SH053-96657 laid open by the Japanese Patent Office. The frequency division circuit concerned is composed of 1/[2n+1] frequency division counter and a flip-flop circuit.
Similarly, an odd-number frequency division circuit is disclosed in Provisional Publication No. SHO57-26930. The frequency division circuit is composed of a shift register, a flip-flop circuit and a logic circuit.
Similarly, an odd-number frequency divider is disclosed in Provisional Publication No. SHO63-79421. The frequency divider concerned is composed of a counter circuit, a shift register, a logic circuit and a 1/2 frequency division circuit.